\section{Related Work}
Recently we have seen a recent trend of moving design abstraction to a higher
level, with an emphasis on \emph{Electronic System Level (ESL)} design
methodologies. Ariki et al.~\cite{Araki2010} proposed a model-based SoC design
flow using ESL environment. Su et al.~\cite{Su2010} and Schafer et
al.~\cite{Schafer2010} presented case studies of ESL design methodologies on
GSM edge algorithm and complex image processing systems, respectively.
Nevertheless, the major research on ESL is targeting at conventional 2D SoC
architecture.

Cost analysis for 3D ICs have been addressed in several existing literatures.
Mercier et al~\cite{Mercier2006} first looked at the yield modeling of 3D IC
stacking regarding stacking yield loss. Dong et al~\cite{Dong2009} proposed
system-level cost analysis and design exploration for 3D ICs, by estimating the
implementation cost of different stacking options, given the gate count of a
design. Chen et al~\cite{Chen2010} extended the cost analysis of 3D ICs by
considering the testing cost of different design choices.

\vspace{10pt}
\section{Conclusion}

With the adoption of 3D IC technology, designers have more choices in design
space, which makes it harder to have optimal design only by human effort. For
design space exploration, a system-level 3D SoC design and hardware/software
co-synthesis framework is proposed in this paper. Proposed framework aims at
providing designers optimal architectures in a short time with user defined
goal.

We demonstrated our approach can give out optimal design choices combining 3D
partitioning and floorplanning with task allocation and scheduling. Analysis of
system-level cost including 3D bonding cost is presented. The properties
provided by 3D related tools can further influence the synthesis results. A
real world case study using proposed framework is performed and shows the
effectiveness of our proposed methodology.
